ASIC Design Costs Have Nearly Doubled Since FinFET Era, Concentrating Chip Power in Fewer Hands
ASIC design costs have nearly doubled since FinFET adoption in the mid-2010s, with lithography masks at advanced nodes costing tens of millions of dollars. The capital barrier is eliminating academic labs as meaningful chip R&D contributors and consolidating semiconductor leadership among a shrinking pool of well-capitalized players. For tech investors, the resulting moats are durable—but concentration risk rises in step.
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